Avanti Recruitment have partnered with a collaborative engineering company based in Cambridge to recruit verification engineers from junior through to principal level. The company are producing high quality open source silicon designs, working on projects with global giants in the technology industry.
They were one of the founding members of RISC-V international and have gained great respect within the industry. They’re looking for verification engineers with a background in SV/UVM to join their team, focusing on verifying open source designs for future versions of their current projects.
To be successful in this role you’ll need:
They were one of the founding members of RISC-V international and have gained great respect within the industry. They’re looking for verification engineers with a background in SV/UVM to join their team, focusing on verifying open source designs for future versions of their current projects.
To be successful in this role you’ll need:
- A minimum of 2 years’ experience in verification
- Experience with Systemverilog/UVM
- An understanding of RISC-V architecture
- Experience with Python
- An understanding of Formal verification is a big plus
